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authorPierre Gondois <[email protected]>2022-11-07 16:57:09 +0100
committerBjorn Andersson <[email protected]>2022-12-29 10:22:11 -0600
commit9435294c6517dc70bb608505b79097a58ea7c6a3 (patch)
tree8bb586c79667c0b42efe50d283fb1934645bf398 /tools/perf/scripts/python/export-to-postgresql.py
parentdcc7cd5c46ca5e7bb8e4910ed8259597439c7246 (diff)
arm64: dts: qcom: Update cache properties
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. About msm8953.dtsi: According to the Devicetree Specification v0.3, s3.7.3 'Internal (L1) Cache Properties', cache-unified: If present, specifies the cache has a unified or- ganization. If not present, specifies that the cache has a Harvard architecture with separate caches for instructions and data. Plus, the 'cache-level' property seems to be reserved to higher cache levels (cf s3.8). To describe a l1 data/instruction cache couple, no cache information should be described. Remove the l1 cache nodes. Signed-off-by: Pierre Gondois <[email protected]> [bjorn: Moved "qcom" to $subject prefix] Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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