diff options
| author | Ilya Bakoulin <[email protected]> | 2019-03-28 14:43:29 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-06-22 09:34:09 -0500 |
| commit | 8e27a2d4cd76095c80dbbf63548175659d4b9d76 (patch) | |
| tree | d7ef5c0d536ba6ed87877d95775da7cdda2147dd /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 0213541d4b6b241a83611dd8324af024f87b5368 (diff) | |
drm/amd/display: Fix DCFCLK and SOCCLK not set
[Why]
If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML
calculations, which ended up causing an assert.
[How]
Initialize dcfclk_mhz and socclk_mhz values according to the
voltage level.
Signed-off-by: Ilya Bakoulin <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions