aboutsummaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python/export-to-postgresql.py
diff options
context:
space:
mode:
authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>2023-12-07 14:10:23 -0800
committerRadhakrishna Sripada <radhakrishna.sripada@intel.com>2023-12-08 10:59:51 -0800
commit877fd09a120d0acee073fbada79fad2ab35396c2 (patch)
tree5d488d26d0338a92adb53803b30663639fc17a62 /tools/perf/scripts/python/export-to-postgresql.py
parentc6117b33a173717714a8dbbf9d14ca85db79725e (diff)
drm/i915/mtl: Use port clock compatible numbers for C20 phy
In C20 pll_state link_bit_rate and clock fields are bit redundant. Since many of the helpers assume the clock values, which are different from link_bit_rate for dp2.0, convert the helpers to use the numbers that are compatible with link_bit_rate. Currently link_bit_rate is compatible with crtc_state->port_clock. The function intel_c20pll_calc_port_clock returns the number which is compatible with crtc_state->port_clock. In order to avoid extra conversions b/ween clock and link_bit_rate, remove "clock" field from the C20 pll_state and then rename "link_bit_rate" as "clock". While at it rely on crtc_state->port_clock during C20 Pll programming. Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231207221025.2032207-2-radhakrishna.sripada@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions