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| author | Apurva Nandan <a-nandan@ti.com> | 2023-05-04 13:33:04 +0530 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2023-06-15 11:05:46 +0530 |
| commit | 8758109d135401c8afea0d0e3c51e7a52c843b7b (patch) | |
| tree | d9bb837e1e7739c90bd0022144d2aee8d35c747f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 2dc39c564982f2ca77a9589a3d9906ecaf5a42e4 (diff) | |
arm64: dts: ti: k3-j784s4-mcu-wakeup: Add FSS OSPI0 and FSS OSPI1
TI K3 J784S4 has the Cadence OSPI controllers OSPI0 and OSPI1 on FSS
bus for interfacing with OSPI flashes. Add the nodes to allow using
SPI flashes.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20230504080305.38986-2-a-nandan@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions