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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2021-11-12 08:10:00 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 11:34:56 +0100 |
| commit | 86e122c0754951094a3857870ad9f4022e056f6b (patch) | |
| tree | 2c36188978419b83b784cce13725e3c23f21093b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | e5f7e81ee430acb6d1fa9a6323fe645bd52e0b9c (diff) | |
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
Core clock "I" is sourced from CPG_PL1_DDIV which controls CPU
frequency. Define CPG_PL1_DDIV, so that we can register it as a
clock divider in later patch.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211112081003.15453-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions