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| author | Suman Anna <s-anna@ti.com> | 2020-08-25 12:21:42 -0500 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2020-08-31 06:31:23 -0500 |
| commit | 804a4cc7fe3cc7207b25c63f21ea82f1b77d19ae (patch) | |
| tree | ba8d9424641fffba2afe6fe211bc8ff617bc2df4 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | e379ba840a7e2c8fb275722226154339077b8f37 (diff) | |
arm64: dts: ti: k3-j721e-main: Add C71x DSP node
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.
The following firmware name is used by default for the C71x core,
and can be overridden in a board dts file if desired:
C71x_0 DSP: j7-c71_0-fw
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-6-s-anna@ti.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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