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| author | Yakir Yang <ykk@rock-chips.com> | 2016-02-15 19:10:11 +0800 |
|---|---|---|
| committer | Yakir Yang <ykk@rock-chips.com> | 2016-04-05 10:13:02 +0800 |
| commit | 793ce4eb84ea2f2c3ebb97aab1ba8a4ce0561812 (patch) | |
| tree | fdf9a754e19100c6179362e1b9692680ecff78e6 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 40fc7ce7db770e9e05032be5eefc183690afb5b8 (diff) | |
drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions