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authorArnd Bergmann <[email protected]>2016-02-01 11:19:10 +0100
committerStephen Boyd <[email protected]>2016-02-02 11:53:17 -0800
commit7001ec560a82d1cc2ba5c0c9ac1f7fcca820b27e (patch)
tree95771c8568f7491e8ff3850503fd4c8cf6de7c3d /tools/perf/scripts/python/export-to-postgresql.py
parente8f0e68ec0802dc840e29e0fabdcfdc39aa2a8fb (diff)
clk: vt8500: don't return possibly uninitialized data
The clk-vt8500.c driver would previously enter an endless loop when invalid settings got requested, this was now fixed. However, the driver will now return uninitialized data for a subset of those cases instead, as the gcc correctly warns: clk/clk-vt8500.c: In function 'wm8650_find_pll_bits': clk/clk-vt8500.c:423:12: error: 'best_div2' may be used uninitialized in this function [-Werror=maybe-uninitialized] *divisor2 = best_div2; ^ clk/clk-vt8500.c:422:12: error: 'best_div1' may be used uninitialized in this function [-Werror=maybe-uninitialized] *divisor1 = best_div1; ^ clk/clk-vt8500.c:421:14: error: 'best_mul' may be used uninitialized in this function [-Werror=maybe-uninitialized] *multiplier = best_mul; This reworks the error handling in the driver so we now return -EINVAL from clk_round_rate() and clk_set_rate() when we get impossible inputs. Signed-off-by: Arnd Bergmann <[email protected]> Fixes: 090341b0a95d ("clk: vt8500: fix sign of possible PLL values") Signed-off-by: Stephen Boyd <[email protected]>
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