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authorStanley Chu <[email protected]>2019-12-30 13:32:30 +0800
committerMartin K. Petersen <[email protected]>2020-01-02 21:57:45 -0500
commit5d74e18edd7bdb1fcc35bd115af720ebfb8c5cf0 (patch)
treea476699e2d556d3eaf831582f0aa8b2ca867166e /tools/perf/scripts/python/export-to-postgresql.py
parent8588c6b032176feb5fcef8f56a1140feded5d6c4 (diff)
scsi: ufs-mediatek: configure and enable clk-gating
Enable clk-gating with customized delayed timer value in MediaTek Chipsets. Cc: Alim Akhtar <[email protected]> Cc: Avri Altman <[email protected]> Cc: Bart Van Assche <[email protected]> Cc: Bean Huo <[email protected]> Cc: Can Guo <[email protected]> Cc: Florian Fainelli <[email protected]> Cc: Matthias Brugger <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Alim Akhtar <[email protected]> Signed-off-by: Stanley Chu <[email protected]> Signed-off-by: Martin K. Petersen <[email protected]>
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