drm/amdgpu: Read clock counter via MMIO to reduce delay (v5)

[Why]
GPU timing counters are read via KIQ under sriov, which will introduce
a delay.

[How]
It could be directly read by MMIO.

v2: Add additional check to prevent carryover issue.
v3: Only check for carryover for once to prevent performance issue.
v4: Add comments of the rough frequency where carryover happens.
v5: Remove mutex and gfxoff ctrl unused with current timing registers.

Signed-off-by: YuBiao Wang <[email protected]>
Acked-by: Horace Chen <[email protected]>
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Monk Liu <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Reviewed-by: Luben Tuikov <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

0 files changed, 0 insertions, 0 deletions