diff options
| author | Anshuman Khandual <anshuman.khandual@arm.com> | 2020-05-19 15:10:38 +0530 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-05-21 15:47:11 +0100 |
| commit | 2a5bc6c47bc3b1bcdab5bef7e74fbb74d17dc618 (patch) | |
| tree | 8fe0494053779f4c02edd7eddab40318c190ea5c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | f73531f0257f6bac44a8c9d5c2f3a3ccaea3d1e9 (diff) | |
arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register
ID_ISAR0[31..28] bits are RES0 in ARMv8, Reserved/UNK in ARMv7. Currently
these bits get exposed through generic_id_ftr32[] which is not desirable.
Hence define an explicit ftr_id_isar0[] array for ID_ISAR0 register where
those bits can be hidden.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1589881254-10082-2-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions