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authorErwan Le Ray <[email protected]>2021-03-04 17:22:59 +0100
committerGreg Kroah-Hartman <[email protected]>2021-03-10 09:34:10 +0100
commit25a8e7611da5513b388165661b17173c26e12c04 (patch)
tree1b6efb10fc4628895ece9004ba50ac2012a84de4 /tools/perf/scripts/python/export-to-postgresql.py
parentf264c6f6aece81a9f8fbdf912b20bd3feb476a7a (diff)
serial: stm32: fix TX and RX FIFO thresholds
TX and RX FIFO thresholds may be cleared after suspend/resume, depending on the low power mode. Those configurations (done in startup) are not effective for UART console, as: - the reference manual indicates that FIFOEN bit can only be written when the USART is disabled (UE=0) - a set_termios (where UE is set) is requested firstly for console enabling, before the startup. Fixes: 84872dc448fe ("serial: stm32: add RX and TX FIFO flush") Signed-off-by: Erwan Le Ray <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
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