diff options
| author | Dongwon Kim <dongwon.kim@intel.com> | 2016-03-16 18:06:13 -0700 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2016-04-11 13:02:23 +0300 |
| commit | 25a56705332add0363e47b3a0eca001d6fbd5bec (patch) | |
| tree | 99a0ba2d29091cb655bc44aee57a67c37162c601 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | c0ead7039affb0f7ce7b734655419d43142e8f5e (diff) | |
drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
For BXT, description of polarities of PORT_PLL_REF_SEL
has been reversed for newer Gen9LP steppings according to the
recent update in Bspec. This bit now should be set for
"Non-SSC" mode for all Gen9LP starting from B0 stepping.
v2: Only B0 and newer stepping should be affected by this
change.
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94866
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458176773-26925-1-git-send-email-dongwon.kim@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions