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| author | Adam Skladowski <a39.skl@gmail.com> | 2023-08-12 13:24:48 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-09-13 12:07:59 -0700 |
| commit | 1fa2d1a887c763246662a88e203d69b36052770c (patch) | |
| tree | d881cba2bfd63e3504d5bb2664348a8d33e90e2b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | de37ca2dc98607e74522d8f243aa7feac74577c5 (diff) | |
clk: qcom: hfpll: Add MSM8976 PLL data
Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL.
Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz.
For simplicity only add second range as smaller frequencies can be obtained
via apcs divider or safe parent this also saves us
a hassle of reconfiguring VCO bit and config_val.
A72 and CCI cluster only use single frequency range with their
outputs/post_dividers/vco_bits being static.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230812112534.8610-6-a39.skl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions