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authorLi Zhong <zhong@linux.vnet.ibm.com>2016-11-11 12:57:35 +0800
committerPaul Mackerras <paulus@ozlabs.org>2017-01-27 10:27:02 +1100
commit17d48610ae0fa218aa386b16a538c792991a3652 (patch)
tree344f26e281c3111d92f1a43c20cce00fd8739eb7 /tools/perf/scripts/python/export-to-postgresql.py
parentbf5a71d53835110d46d33eb5335713ffdbff9ab6 (diff)
KVM: PPC: Book 3S: XICS: Implement ICS P/Q states
This patch implements P(Presented)/Q(Queued) states for ICS irqs. When the interrupt is presented, set P. Present if P was not set. If P is already set, don't present again, set Q. When the interrupt is EOI'ed, move Q into P (and clear Q). If it is set, re-present. The asserted flag used by LSI is also incorporated into the P bit. When the irq state is saved, P/Q bits are also saved, they need some qemu modifications to be recognized and passed around to be restored. KVM_XICS_PENDING bit set and saved should also indicate KVM_XICS_PRESENTED bit set and saved. But it is possible some old code doesn't have/recognize the P bit, so when we restore, we set P for PENDING bit, too. The idea and much of the code come from Ben. Signed-off-by: Li Zhong <zhong@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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