dmaengine: pl330: Align DMA memcpy operations to MFIFO width

The algorithm used for programming the DMA Controller doesn't take into
consideration the requirements of transfers that are not aligned to the
bus width. This failure may result in DMA transferring one too few MFIFO
entries (so too few bytes are copied) or the DMA trying to write one too
many MFIFO entries and hanging because this is never provided.

See "MFIFO Usage Overview" chapter in the the TRM for "CoreLink DMA
Controller DMA-330", Revision r1p1.

We work around these shortcomings by making sure we pick a burst size
and length which ensures no bursts straddle an MFIFO entry.

Signed-off-by: Jon Medhurst <[email protected]>
[squashed linker error "undefined reference to `__aeabi_uldivmod]
Reported-by: kbuild test robot <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>

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