diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2019-09-27 21:09:21 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-12-20 15:02:15 +0100 |
| commit | 0d67c0340a60829c5c1b7d09629d23bbd67696f3 (patch) | |
| tree | cc7fd9d1dea43e9239d3c75460b22ea930dc9803 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 03975b72b4ac474f83edde145bcf152c7d2183cd (diff) | |
clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
clk_register_composite() when registering the RPC[D2] clocks...
Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/be27a344-d8bf-9e0c-8950-2d1b48498496@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions