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| author | Mark Rutland <mark.rutland@arm.com> | 2015-03-24 15:10:21 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-03-24 15:13:58 +0000 |
| commit | 0c20856c260236b96f54c452d38dbe1348ed34d2 (patch) | |
| tree | b55c273e2889304f54643ee4b90325e92fb4190c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | d5efd9cc9cf2e422d064c912c7d5d985f52c1b2c (diff) | |
arm64: head.S: ensure idmap_t0sz is visible
We write idmap_t0sz with SCTLR_EL1.{C,M} clear, but we only have the
guarnatee that the kernel Image is clean, not invalid in the caches, and
therefore we might read a stale value once the MMU is enabled.
This patch ensures we invalidate the corresponding cacheline after the
write as we do for all other data written before we set SCTLR_EL1.{C.M},
guaranteeing that the value will be visible later. We rely on the DSBs
in __create_page_tables to complete the maintenance.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
CC: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions