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authorHuicong Xu <[email protected]>2023-06-15 17:10:23 +0000
committerVinod Koul <[email protected]>2023-07-12 22:27:43 +0530
commitf79b812baf21366fae975b29f671258fb38d643b (patch)
treeb05ed3dc1c102d38b202668cef7088de237e1b11 /tools/perf/scripts/python/event_analyzing_sample.py
parent19a1d46bd699940a496d3b0d4e142ef99834988c (diff)
phy/rockchip: inno-hdmi: force set_rate on power_on
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by: Huicong Xu <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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