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| author | Chris Brandt <chris.brandt@renesas.com> | 2017-02-16 18:55:55 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2017-03-17 10:01:28 +0000 |
| commit | f08578e6da96043ec07a695fb6f4cba27a9d22d7 (patch) | |
| tree | 6337728f202b5b2fafcea8ebf497afe708f4fc8a /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | a96bb197693eb9e7a7221867bd944ccd6b6e12e6 (diff) | |
ARM: 8661/1: dts: r7s72100: add l2 cache
Note that early-bresp-disable and full-line-zero-disable are required
because the sideband signals between the CPU and L2C were not connected
in this SoC.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions