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| author | Tony Lindgren <[email protected]> | 2019-05-27 04:51:54 -0700 |
|---|---|---|
| committer | Tony Lindgren <[email protected]> | 2019-05-28 05:19:15 -0700 |
| commit | eec26555ae9bf69da8bfe90cacdbc85d7a23391b (patch) | |
| tree | 5bd8636931cff896b1ddd44f22c214fa52b868c3 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | bd808f9a442301e493fe0bb3168774b4da7bb605 (diff) | |
bus: ti-sysc: Enable interconnect target module autoidle bit on enable
For interconnect target modules with autoidle bit wired, we need to manage
it for enable and disable.
Tested-by: Keerthy <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions