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| author | Martin Povišer <[email protected]> | 2022-06-30 09:51:33 +0200 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2022-07-07 17:16:33 +0100 |
| commit | d1a10f1b48202e2d183cce144c218a211e98d906 (patch) | |
| tree | 6706e7f6af3a74076076768128aad1abcc11a9cf /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | cd10bb89b0d57bca98eb75e0444854a1c129a14e (diff) | |
ASoC: tas2764: Fix and extend FSYNC polarity handling
Fix setting of FSYNC polarity in case of LEFT_J and DSP_A/B formats.
Do NOT set the SCFG field as was previously done, because that is not
correct and is also in conflict with the "ASI1 Source" control which
sets the same SCFG field!
Also add support for explicit polarity inversion.
Fixes: 827ed8a0fa50 ("ASoC: tas2764: Add the driver for the TAS2764")
Signed-off-by: Martin Povišer <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions