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| author | Tobias Waldekranz <[email protected]> | 2022-02-13 19:51:54 +0100 |
|---|---|---|
| committer | Jakub Kicinski <[email protected]> | 2022-02-14 21:13:54 -0800 |
| commit | d0b78ab1ca357628ffb92cf8a0af00b4ffdc4e3b (patch) | |
| tree | 9ac673c5c97ff4316d0ee1d70f48f9bf3c817268 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 12d8c11198af191d06d02b01624d84c669ef7231 (diff) | |
net: dsa: mv88e6xxx: Fix validation of built-in PHYs on 6095/6097
These chips have 8 built-in FE PHYs and 3 SERDES interfaces that can
run at 1G. With the blamed commit, the built-in PHYs could no longer
be connected to, using an MII PHY interface mode.
Create a separate .phylink_get_caps callback for these chips, which
takes the FE/GE split into consideration.
Fixes: 2ee84cfefb1e ("net: dsa: mv88e6xxx: convert to phylink_generic_validate()")
Signed-off-by: Tobias Waldekranz <[email protected]>
Reviewed-by: Russell King (Oracle) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jakub Kicinski <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions