aboutsummaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python/event_analyzing_sample.py
diff options
context:
space:
mode:
authorStanislav Lisovskiy <[email protected]>2019-07-12 11:19:38 +0300
committerJani Nikula <[email protected]>2019-08-05 11:30:54 +0300
commitce52ad5dd52cfaf3398058384e0ff94134bbd89c (patch)
treeccd4dd49cf70679ba90202a477cec8439ee7bcac /tools/perf/scripts/python/event_analyzing_sample.py
parentb40d73784ffc33f3c6431e7ceec3b20fffcd95c3 (diff)
drm/i915: Fix wrong escape clock divisor init for GLK
According to Bspec clock divisor registers in GeminiLake should be initialized by shifting 1(<<) to amount of correspondent divisor. While i915 was writing all this time that value as is. Surprisingly that it by accident worked, until we met some issues with Microtech Etab. v2: Added Fixes tag and cc v3: Added stable to cc as well. Signed-off-by: Stanislav Lisovskiy <[email protected]> Reviewed-by: Vandita Kulkarni <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108826 Fixes: bcc657004841 ("drm/i915/glk: Program txesc clock divider for GLK") Cc: Deepak M <[email protected]> Cc: Madhav Chauhan <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions