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authorRichard Fitzgerald <[email protected]>2021-08-05 17:11:10 +0100
committerMark Brown <[email protected]>2021-08-05 23:33:45 +0100
commitc76d572c1ec82e305c97219e28952966958bc31a (patch)
tree441f362a356f36dbc38c4b2938ba01f1476938ce /tools/perf/scripts/python/event_analyzing_sample.py
parent24cdbb79bbfe690f7fe87507dd0489670eddb5b0 (diff)
ASoC: cs42l42: Assume 24-bit samples are in 32-bit slots
If the machine driver doesn't call snd_soc_dai_set_sysclk() the SCLK is assumed to be sample_rate * sample_bits * 2 (that is, the rate necessary for a standard I2S frame). But 24-bit samples can be sent in either a 24-bit slot or a 32-bit slot. If the PLL is configured for a 24-bit slot, but a 32-bit slot is used, cs42l42 will be overclocked. Ultimately it is the machine driver's responsibilty to call snd_soc_dai_set_sysclk() if SLK will be different from the standard I2S rate. However, it is convenient to assume 32-bit slots to allow this common case without needing special machine driver support. The machine driver then only has to set SCLK if the slots are 24-bit, but if it fails to do this cs42l42 won't be overclocked. Signed-off-by: Richard Fitzgerald <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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