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| author | Madhavan Srinivasan <[email protected]> | 2020-07-17 10:38:16 -0400 |
|---|---|---|
| committer | Michael Ellerman <[email protected]> | 2020-07-22 21:56:41 +1000 |
| commit | c718547e4a92d74089f862457adf1f617c498e16 (patch) | |
| tree | 736bc5079b79f612d722cf831c9ca0f160d64c67 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 9d4fc86dcd510dab5521a6c891f9bf379b85a7e0 (diff) | |
powerpc/perf: Add support for ISA3.1 PMU SPRs
PowerISA v3.1 includes new performance monitoring unit(PMU)
special purpose registers (SPRs). They are
Monitor Mode Control Register 3 (MMCR3)
Sampled Instruction Event Register 2 (SIER2)
Sampled Instruction Event Register 3 (SIER3)
MMCR3 is added for further sampling related configuration
control. SIER2/SIER3 are added to provide additional
information about the sampled instruction.
Patch adds new PPMU flag called "PPMU_ARCH_31" to support handling of
these new SPRs, updates the struct thread_struct to include these new
SPRs, include MMCR3 in struct mmcr_regs. This is needed to support
programming of MMCR3 SPR during event_enable/disable. Patch also adds
the sysfs support for the MMCR3 SPR along with SPRN_ macros for these
new pmu SPRs.
Signed-off-by: Madhavan Srinivasan <[email protected]>
[mpe: Rename to PPMU_ARCH_31 as noted by jpn]
Signed-off-by: Michael Ellerman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions