diff options
| author | Thomas Gleixner <[email protected]> | 2015-05-19 00:00:58 +0000 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2015-05-27 09:17:41 +0200 |
| commit | bf926731e1585ccad029ca2fad1444fee082b78d (patch) | |
| tree | 3565ea28fe99cc3b1ef04fab5b9069d4f95f5695 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 43d0c2f6dcd07ffc0de658a7fbeeb63c806e9caa (diff) | |
perf/x86/intel/cqm: Add storage for 'closid' and clean up 'struct intel_pqr_state'
'closid' (CLass Of Service ID) is used for the Class based Cache
Allocation Technology (CAT). Add explicit storage to the per cpu cache
for it, so it can be used later with the CAT support (requires to move
the per cpu data).
While at it:
- Rename the structure to intel_pqr_state which reflects the actual
purpose of the struct: cache values which go into the PQR MSR
- Rename 'cnt' to rmid_usecnt which reflects the actual purpose of
the counter.
- Document the structure and the struct members.
Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Acked-by: Matt Fleming <[email protected]>
Cc: Kanaka Juvva <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Vikas Shivappa <[email protected]>
Cc: Will Auld <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions