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authorRuss Weight <[email protected]>2021-03-23 15:46:50 -0700
committerMoritz Fischer <[email protected]>2021-03-24 11:15:04 -0700
commit9a8d3cda8daf54b1f8e67ccb360876379b7e7895 (patch)
tree6b3edaecfaf44801b5bba4e4428b1776ba2bd542 /tools/perf/scripts/python/event_analyzing_sample.py
parent6f1e376cfc6864a2f46538db909bbd5253c3c146 (diff)
fpga: dfl: afu: harden port enable logic
Port enable is not complete until ACK = 0. Change __afu_port_enable() to guarantee that the enable process is complete by polling for ACK == 0. Signed-off-by: Russ Weight <[email protected]> Reviewed-by: Tom Rix <[email protected]> Reviewed-by: Matthew Gerlach <[email protected]> Acked-by: Wu Hao <[email protected]> Signed-off-by: Moritz Fischer <[email protected]>
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