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| author | Esben Haabendal <esben@geanix.com> | 2024-08-14 12:37:26 +0200 |
|---|---|---|
| committer | Robert Foss <rfoss@kernel.org> | 2024-08-19 15:36:47 +0200 |
| commit | 8a879141dcd15d2db876ce3adf88b9b01650b7fa (patch) | |
| tree | e588d924616ae0e42468c06e36ef481bd67781a4 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 11c742bb5a26d4adc873f6e6e2b69a59e1eae285 (diff) | |
drm/bridge: nwl-dsi: Use vsync/hsync polarity from display mode
Using the correct bit helps. The documentation specifies bit 0 in both
registers to be controlling polarity of dpi_vsync_input and
dpi_hsync_input polarity. Bit 1 is reserved, and should therefore not be
set.
Tested with panel that requires active high vsync and hsync.
Signed-off-by: Esben Haabendal <esben@geanix.com>
Reviewed-by: Robert Foss <rfoss@kernel.org>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240814-nwl-dsi-sync-polarity-v1-1-ee198e369196@geanix.com
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions