clk: exynos5420: Add IDs for clocks used in DISP1 power domain

When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.

So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:

ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)

Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.

Signed-off-by: Javier Martinez Canillas <[email protected]>
Acked-by: Sylwester Nawrocki <[email protected]>
Acked-by: Michael Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>

0 files changed, 0 insertions, 0 deletions