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| author | Bartlomiej Zolnierkiewicz <[email protected]> | 2015-01-24 14:05:50 +0900 |
|---|---|---|
| committer | Kukjin Kim <[email protected]> | 2015-01-30 08:38:52 +0900 |
| commit | 865e8b76a04d018f23d809ebf735c52105e3adb2 (patch) | |
| tree | 17e4a12f8932e69b6c96feabf853e19203fee0b1 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff) | |
ARM: EXYNOS: apply S5P_CENTRAL_SEQ_OPTION fix only when necessary
Commit c2dd114d2486 ("ARM: EXYNOS: fix register setup for AFTR mode
code") added S5P_CENTRAL_SEQ_OPTION register setup fix for all
Exynos SoCs to AFTR mode code-path. It turned out that for coupled
cpuidle AFTR mode on Exynos4210 (added by the next patch) applying
this fix causes lockup so enable it in the AFTR mode code-path only
on SoCs that require it (in the suspend code-path it can be always
applied like it was before commit c2dd114d2486 ("ARM: EXYNOS: fix
register setup for AFTR mode code")
Cc: Daniel Lezcano <[email protected]>
Cc: Colin Cross <[email protected]>
Cc: Tomasz Figa <[email protected]>
Signed-off-by: Bartlomiej Zolnierkiewicz <[email protected]>
Acked-by: Kyungmin Park <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions