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authorMatt Roper <[email protected]>2023-10-06 11:23:22 -0700
committerRodrigo Vivi <[email protected]>2023-12-21 11:42:57 -0500
commit811aa4d2074a9e64baeaa4bbc2773ead6247f101 (patch)
tree0ee570b3a26d2bc4c8f54a09eae82d7924b7bb3f /tools/perf/scripts/python/event_analyzing_sample.py
parentcf0b9e94c8c755ae94787d638c655bb38e7a8048 (diff)
drm/xe/xe2: Program PAT tables
The PAT tables become significantly more complicated on Xe2 platforms. They now control L3, L4, and coherency settings, as well as additional characteristics such as compression. Aside from the main PAT table, there's an additional register that also needs to be programmed with PAT settings for PCI Address Translation Services. Bspec: 71582 Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Balasubramani Vivekanandan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
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