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| author | Ville Syrjälä <[email protected]> | 2024-03-06 06:08:04 +0200 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2024-03-07 18:14:37 +0200 |
| commit | 810e4519a1b34b5a0ff0eab32e5b184f533c5ee9 (patch) | |
| tree | b55284ba2bca416612318a25b5f9fbf5a361775f /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 3d81fceb60f20fe2ceed2198636ee6dc9ef46775 (diff) | |
drm/i915/vrr: Generate VRR "safe window" for DSB
Looks like TRANS_CHICKEN bit 31 means something totally different
depending on the platform:
TGL: generate VRR "safe window" for DSB
ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
So far we've only set this on ADL/DG2, but when using DSB+VRR
we also need to set it on TGL.
And a quick test on MTL says it doesn't need this bit for either
of those purposes, even though it's still documented as valid
in bspec.
Cc: [email protected]
Fixes: 34d8311f4a1c ("drm/i915/dsb: Re-instate DSB for LUT updates")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9927
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Animesh Manna <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions