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authorLiu Ying <Ying.Liu@freescale.com>2015-02-12 14:01:28 +0800
committerShawn Guo <shawn.guo@linaro.org>2015-03-02 20:52:09 +0800
commit721fee59d26e46700476f4c70572e9e0f1cc8fd3 (patch)
tree77f2d35c158697743f91366d5c28a8df67465ed6 /tools/perf/scripts/python/event_analyzing_sample.py
parent974a7115986ee5d0b2db9cc8cd551e6f88e01378 (diff)
ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the hsi_tx_sel clock's output and the video_27m clock's output. So, this patch changes the hsi_tx clock to be a shared clock gate. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
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