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author | Lad Prabhakar <[email protected]> | 2022-10-25 23:06:28 +0100 |
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committer | Geert Uytterhoeven <[email protected]> | 2022-10-28 14:22:59 +0200 |
commit | 49669da644cf000eb79dbede55bd04acf3f2f0a0 (patch) | |
tree | bace807eb076056cf10450caa296d41e70d291bd /tools/perf/scripts/python/event_analyzing_sample.py | |
parent | 5b093eb67e36182f3bad4375c79278b7236d3bd7 (diff) |
arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property
Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so
that we can share the common parts of the SoC DTSI with the RZ/Five
(RISC-V) SoC and the RZ/G2UL (ARM64) SoC.
This patch adds a new file r9a07g043u.dtsi to separate out RZ/G2UL
(ARM64) SoC specific parts. No functional changes (same DTB).
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions