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| author | Lad Prabhakar <[email protected]> | 2022-10-28 17:59:20 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-11-10 16:36:34 +0100 |
| commit | 461e1857d6bf15cf5df103383e255f3425ac0038 (patch) | |
| tree | 873bc62a02a53cd4405bb6aaa3f7008ed9cfa798 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 4adb690aa1b41c1e52af579574d1d6aa58da1187 (diff) | |
MAINTAINERS: Add entry for Renesas RISC-V
Add RISC-V architecture as part of ARM/Renesas architecture, as they have
the same maintainers, use the same development collaboration
infrastructure, and share many files.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions