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authorPaul Cercueil <[email protected]>2018-01-16 16:47:53 +0100
committerJames Hogan <[email protected]>2018-01-18 22:05:13 +0000
commit268db077ac47d3b5d8e3a768bf9dc5cb32ce6074 (patch)
tree59380382f525ff4869a1ac1d5b586fde3059ea48 /tools/perf/scripts/python/event_analyzing_sample.py
parente6cfa64375d34a6c8c1861868a381013b2d3b921 (diff)
clk: ingenic: support PLLs with no bypass bit
The second PLL of the JZ4770 does not have a bypass bit. This commit makes it possible to support it with the current common CGU code. Signed-off-by: Paul Cercueil <[email protected]> Acked-by: Stephen Boyd <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: Maarten ter Huurne <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/18479/ Signed-off-by: James Hogan <[email protected]>
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