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| author | Aneesh Kumar K.V <[email protected]> | 2016-07-13 15:05:21 +0530 |
|---|---|---|
| committer | Michael Ellerman <[email protected]> | 2016-07-17 16:42:50 +1000 |
| commit | bf16cdf48a5369ba29614a0ade4ae5daf7a9e47c (patch) | |
| tree | 4abc3ff7bb6e15944e9a377bfe4a6064b457a402 /tools/perf/scripts/python/compaction-times.py | |
| parent | 8cd6d3c23e226ec6cb8825e1aa6a391ebda71c72 (diff) | |
powerpc/mm/radix: Update LPCR HR bit as per ISA
PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
to be mirrored in the LPCR register, in addition to the partition table.
This is done to avoid fetching from the table when deciding, among other
things, how to perform transitions to HV mode on some interrupts.
So let's set it up appropriately
Signed-off-by: Aneesh Kumar K.V <[email protected]>
Acked-by: Balbir Singh <[email protected]>
Signed-off-by: Michael Ellerman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/compaction-times.py')
0 files changed, 0 insertions, 0 deletions