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| author | Siddharth Vadapalli <[email protected]> | 2023-07-25 13:00:57 +0530 |
|---|---|---|
| committer | Nishanth Menon <[email protected]> | 2023-08-01 23:46:10 -0500 |
| commit | 7815b2816d146f302f3884ee8e87c7b39fea1ecc (patch) | |
| tree | e28cb489017c4967ef04a4ce4f42f194d412b8d9 /tools/perf/scripts/python/compaction-times.py | |
| parent | 5d55545cc2da8ad320b73705b26a5c0a837b20da (diff) | |
arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports with GESI
The J7 GESI EXP board for J721E Common-Proc-Board supports RGMII mode.
Use the overlay to configure CPSW9G ports in RGMII-RXID mode.
Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses
directly from U-Boot.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Ravi Gunasekaran <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Nishanth Menon <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/compaction-times.py')
0 files changed, 0 insertions, 0 deletions