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| author | Amit Daniel Kachhap <[email protected]> | 2022-11-17 06:16:12 +0100 |
|---|---|---|
| committer | Russell King (Oracle) <[email protected]> | 2022-11-28 11:57:31 +0000 |
| commit | 74c344e6f153dd9ae97c99ad751723e4030d4af9 (patch) | |
| tree | 5b37ac730be36cd7b22a80420d4b6e73fc1f4d67 /tools/perf/scripts/python/compaction-times.py | |
| parent | f424f2c18432f8a2c35ebafb23dd004148bce149 (diff) | |
ARM: 9267/1: Define Armv8 registers in AArch32 state
AArch32 Instruction Set Attribute Register 6 (ID_ISAR6_EL1) and AArch32
Processor Feature Register 2 (ID_PFR2_EL1) identifies some new features
for the Armv8 architecture. This registers will be utilized to add
hwcaps for those cpu features.
These registers are marked as reserved for Armv7 and should be a RAZ.
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Amit Daniel Kachhap <[email protected]>
Signed-off-by: Russell King (Oracle) <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/compaction-times.py')
0 files changed, 0 insertions, 0 deletions