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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2021-02-25 01:47:51 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-03-17 09:14:47 -0700 |
| commit | 3b24cdfc721a5f1098da22f9f68ff5f4a5efccc9 (patch) | |
| tree | 4009b3cbba09a42810a473f363d068f822a72a7c /tools/perf/scripts/python/compaction-times.py | |
| parent | 7bf168c8fe8c6166b5dc10005fe7f250164da0ad (diff) | |
drm/msm/dsi: fix check-before-set in the 7nm dsi_pll code
Fix setting min/max DSI PLL rate for the V4.1 7nm DSI PLL (used on
sm8250). Current code checks for pll->type before it is set (as it is
set in the msm_dsi_pll_init() after calling device-specific functions.
Cc: Jonathan Marek <jonathan@marek.ca>
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'tools/perf/scripts/python/compaction-times.py')
0 files changed, 0 insertions, 0 deletions