diff options
| author | Ville Syrjälä <[email protected]> | 2014-02-11 19:52:06 +0200 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2014-02-11 23:00:47 +0100 |
| commit | f66fab8e1cd6b3127ba4c5c0d11539fbe1de1e36 (patch) | |
| tree | 13024a866349329c4940784f46cc03bae02d9184 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 753b1ad4a281b0663329409d410243e91825c323 (diff) | |
drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB
According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
in a single cacheline. Make sure that happens.
v2: Use intel_ring_begin_cacheline_safe()
v3: Use intel_ring_cacheline_align() (Chris)
Cc: Bjoern C <[email protected]>
Cc: Alexandru DAMIAN <[email protected]>
Cc: Enrico Tagliavini <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053
Signed-off-by: Ville Syrjälä <[email protected]>
Cc: [email protected]
Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions