ARM: 5756/1: ep93xx: introduce clk parent

The clock generation system in the ep93xx uses two external oscillator's
and two internal PLLs to derive all the internal clocks.  Many of these
internal clocks can be stopped to save power.

This introduces a "parent" hierarchy for the clocks so that the users
count can be correctly tracked for power management.

The "parent" for the video clock can either be one of the PLL outputs
or the external oscillator.  In order to correctly track the "parent"
for the video clock calc_clk_div() needed to be modified.  It now
returns an error code if the desired rate cannot be generated.

Signed-off-by: H Hartley Sweeten <[email protected]>
Acked-by: Ryan Mallon <[email protected]>
Signed-off-by: Russell King <[email protected]>

0 files changed, 0 insertions, 0 deletions