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| author | Emilio López <[email protected]> | 2013-12-23 00:32:34 -0300 |
|---|---|---|
| committer | Emilio López <[email protected]> | 2013-12-28 17:08:06 -0300 |
| commit | d838ff33ec3a6262f44476d8edc0303acdc16580 (patch) | |
| tree | 0c700acae95db629e0e085bc4608752e4f77b515 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | edaf3fb580df7f6c510699664f51485030a29f17 (diff) | |
clk: sunxi: add gating support to PLL1
This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.
Signed-off-by: Emilio López <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions