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| author | Ira Weiny <ira.weiny@intel.com> | 2024-04-26 20:34:01 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2024-05-01 09:24:08 -0700 |
| commit | c19ac30eda3a1d14d4883de0ea214b6c5c96a9b4 (patch) | |
| tree | 08982a521b1b02e7c041140b677f31e46bfc6bff /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 5e4a264bf8b55d5a1b4c8cd96ac10b99f98d7487 (diff) | |
cxl/pci: Process CPER events
If the firmware has configured CXL event support to be firmware first
the OS will receive those events through CPER records. The CXL layer has
unique DPA to HPA knowledge and existing event trace parsing in
place.[0]
Add a CXL CPER work item and register it with the GHES code to process
CPER events.
Link: http://lore.kernel.org/r/cover.1711598777.git.alison.schofield@intel.com [0]
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Link: https://lore.kernel.org/r/20240426-cxl-cper3-v4-2-58076cce1624@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions