diff options
| author | Mark Langsdorf <[email protected]> | 2013-01-28 16:13:13 +0000 |
|---|---|---|
| committer | Rafael J. Wysocki <[email protected]> | 2013-02-02 00:01:15 +0100 |
| commit | b5964708532f4713e9cfb1b8b1a6ac8544fc66af (patch) | |
| tree | ac0b962debf44ef6a15a6ea0a652633f1afe372f /tools/perf/scripts/python/check-perf-trace.py | |
| parent | bd603455f366bd66a5e1870bc285c05c9cb6a72d (diff) | |
clk / highbank: Prevent glitches in non-bypass reset mode
The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.
Signed-off-by: Mark Langsdorf <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions