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authorMartin Leung <[email protected]>2022-05-13 17:40:42 -0400
committerAlex Deucher <[email protected]>2022-07-05 16:10:45 -0400
commit90f33674a0756a6f0907b8f6350cec3f7be4032c (patch)
tree84c94aa2702e43a0f9d706e50b6798cda26b7ac1 /tools/perf/scripts/python/check-perf-trace.py
parent85f4bc0c333ceed24cbc9f69a2a77fab1ae3d4d1 (diff)
drm/amd/display: Prepare for new interfaces
[WHY]: Lut pipeline will be hooked up differently in some asics need to add new interfaces and missing registers. [HOW]: Add missing registers and hook up programming from DPP for pre-blend lut. Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Martin Leung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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