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authorjason-jh.lin <[email protected]>2022-04-19 11:32:34 +0800
committerMatthias Brugger <[email protected]>2022-04-19 16:54:44 +0200
commit81c5a41d10b968ea89d5f44fe1e5c2fc70289209 (patch)
tree0aaeb6778c1c588c99fb7573f70f89e025f493a9 /tools/perf/scripts/python/check-perf-trace.py
parent1da90b8a7bae09358569dba26e784d1f471b4aa0 (diff)
dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
In the SoC before, such as mt8173, it has 2 pipelines binding to one mmsys with the same clock driver and the same power domain. In mt8195, there are 4 pipelines binding to 4 different mmsys, such as vdosys0, vdosys1, vppsys0 and vppsys1. Each mmsys uses different clock drivers and different power domain. Since each mmsys has its own mmio base address, they could be identified by their different address during probe time. Signed-off-by: jason-jh.lin <[email protected]> Reviewed-by: CK Hu <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
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