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authorYongqiang Niu <yongqiang.niu@mediatek.com>2022-12-15 15:28:04 +0800
committerJassi Brar <jaswinder.singh@linaro.org>2022-12-18 20:40:29 -0600
commit63f40a7f5dbdb70f8574754475346a9e72ccef6c (patch)
treeb8a5f999e48de7c50e00fa91f7ed0cef4b7644ce /tools/perf/scripts/python/check-perf-trace.py
parent23ba2e7fa282dd8e6c51c284ab1ea184c96c88b2 (diff)
mailbox: mtk-cmdq: add gce software ddr enable private data
if gce work control by software, we need set software enable for MT8186 Soc there is a handshake flow between gce and ddr hardware, if not set ddr enable flag of gce, ddr will fall into idle mode, then gce instructions will not process done. we need set this flag of gce to tell ddr when gce is idle or busy controlled by software flow. 0x48[2:0] means control by software 0x48[18:16] means ddr enable 0x48[2:0] is pre-condition of 0x48[18:16]. if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same time. and only these bits is useful, other bits is useless bits Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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