diff options
| author | Huang, Xiong <[email protected]> | 2012-04-18 22:01:27 +0000 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2012-04-19 20:14:20 -0400 |
| commit | 5cbdcc2f49b4a8372052952799d2cb1de387443b (patch) | |
| tree | 7a6ad570c04d880a26febdc1ad613e8a3a9a90de /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 7f5544d6693ab2593b4f13521a577387f3be6b2f (diff) | |
atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patch
bit MASTER_CTRL_CLK_SEL_DIS could be set before enter suspend
clear it after resume to enable pclk(PCIE clock) switch to
low frequency(25M) in some circumstances to save power.
Signed-off-by: xiong <[email protected]>
Tested-by: Liu David <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions